The present invention relates to a circuit for generating addresses for accessing error detection and correction data from a buffer memory in a CD-ROM or CD-Interactive (CD-i) system, and method therefor.
The data for a CD-ROM or CD-i system consist of 2352 bytes including synchronization 12-bytes per one block. These data are divided into LSB bytes and MSB bytes immediately after synchronization, and undergo error detection and correction for each of two planes. In such a CD-ROM or CD-i system, the parity symbols (P-parity, Q-parity) for the error detection and correction are added to the data in order to improve the reliability of the data processing. The format of the parity is specified in the Yellow Book of the International Specification for the CD-ROM. The decoding of the parity symbols (P-parity, Q-parity) requires the generation of complicated address signals.
The generation of the address signals is accomplished by a method employing a software or hardware. The method employing a software needs long processing time, so that it is difficult to achieve the real time processing. Meanwhile, the method employing a hardware is achieved by the table lock-up system using a ROM into which the addresses are stored for reading as desired. This method, though providing high processing speed, needs a system construction of TTL level, so that the circuit construction is very complicated requiring a large area for integration.